1. Field of the Invention
The present invention relates to a method, a program and system for processing a substrate, such as semiconductor wafer.
2. Description of Related Art
In one example of a photolithographic process in a manufacturing process of semiconductor device, a photoresist film is patterned with sequentially conducted processes: coating photoresist on a target film formed on a semiconductor wafer (hereinafter referred to as “wafer”), exposing the photoresist film to optical radiation having a specific pattern, developing the exposed photoresist film and the like. After that, the target film is patterned through etching the target film using the patterned photoresist film as a mask and removing the photoresist.
To scale down the minimum feature size of a semiconductor device structure, it is being attempted to shorten the wavelength of optical radiation exposing in a photolithographic process. It is, however, hard to scale down the size of, for instance, 32 nm or 45 nm node, depending only on such shortening wavelength.
Japanese Patent No. 2757983 offers a method for scaling down the minimum feature size of a semiconductor device. In the method, different layers on a target film on a wafer are respectively patterned. In particular, first and second patterns of photosensitive films are formed through coating first and second photosensitive films on a target film, and exposing and developing the first and second films, respectively. Then, the target film is patterned by etching using the first and second patterns of photosensitive films as masks.
However, when forming a fine pattern in a target film using the method described in Japanese Patent No. 2757983, it is necessary to accurately align the second pattern relative to the first pattern. There is a high possibility that the two patterns are misaligned. When misalignment occurs, the intended pattern of the target film can not be obtained. Besides, it needs to expose a photosensitive film twice. That makes the cost for manufacturing a semiconductor device high.
U.S. Pat. No. 5,013,680 offers another method for scaling down the minimum feature size of a semiconductor device. In the method, a SiO2 film is formed on a patterned SiN film formed on a target film on a wafer, for instance, with a CVD (chemical vapor deposition) process. A fine pattern of SiO2 film is formed thorough etching back the SiO2 film and removing the SiN film. Then, a target layer is patterned by etching using the SiO2 pattern as a mask.
In a case that a fine pattern of target film is formed using a method described in the United States Patent, each top portion of SiO2 pattern formed on both sides of SiN film has asymmetric shape. Etching with such SiO2 pattern as a mask, a target film having uniform pattern height cannot be obtained.